High-level synthesis (HLS) is an automated design process that creates a circuit design from a high level programming language description of an electronic system. The high level programming language description of the electronic system is an algorithmic description. Examples of high level programming languages include, but are not limited to, C, C++, SystemC, and the like. During HLS, an electronic design automation (EDA) tool operates on the high level programming language description and generates a circuit design. The EDA tool translates the high level programming language description into the circuit design. The circuit design is a hardware description of the electronic system. The circuit design may be a register-transfer level description of the electronic system specified using a hardware description language (HDL).
During HLS, programming language constructs such as functions and/or loops may be analyzed in an effort to generate pipelined circuitry for the body of the construct. Generating pipelined circuitry, however, is dependent upon avoiding read and/or write conflicts to memories in the resulting circuitry. Typically, conflicts are detected through the use of static code analysis as may be performed by a compiler operating on the high level programming language description.
Performing HLS based upon static code analysis tends to be overly conservative. One reason is that static code analysis treats each iteration of a construct such as a loop or execution of a function the same as each other iteration. In generating the circuit design, throughput is reduced until any potential conflicts are avoided in all cases. In effect, the worst case scenario for the occurrence of memory access conflicts, as determined by static analysis, tends to determine throughput of the circuitry specified by the circuit design.